In an electronic device such as a semiconductor element, semiconductor parts such as transistor, resistor and the like are arranged on a substrate. Since those parts must be electrically insulated from each other, it is necessary to form an area separating them. This area is referred to as an “isolation area”. Hitherto, the isolation area has been generally provided by forming an insulating layer selectively on the surface of the semiconductor substrate.
Meanwhile, recently in the field of electronic device technology, the density and the integration degree have been more and more increased. According as the density and the integration degree are becoming higher, it is getting more difficult to form an isolation structure having fineness corresponding to the required integration degree. It is, therefore, desired to provide a new isolation structure satisfying the required fineness. As one of the isolation structures capable of satisfying the requirement, a trench isolation structure is proposed. The trench isolation structure is fabricated by forming fine trenches on a semiconductor substrate and then filling the trenches with insulating material so as to electrically separate the part positioned on one side from that on the other side of each trench. The structure thus electrically separating the parts can reduce the isolation area, as compared with the conventional structure, and accordingly, is effective in achieving the integration degree required in these days.
The trench isolation structure can be formed, for example, according to a self-aligned shallow trench isolation process. This process normally comprises the steps of: coating a composition containing insulating material (hereinafter, referred to as “SOD material”) onto the substrate surface beforehand provided with trenches, so as to fill the trenches with the composition; hardening the SOD material by firing or the like, so as to convert the SOD material to form an insulating layer; removing excess of the layer on the substrate surface by chemical mechanical polishing (hereinafter, referred to as “CMP”); and flattening the substrate surface by wet-etching.
For the above process, various etching solutions have been studied. The simplest solutions are, for example, an aqueous hydrofluoric acid solution and a hydrofluoric acid buffer. Further, other examples of the solutions include an isopropyl alcohol-added aqueous hydrofluoric acid solution (disclosed in Patent document 1) and a solution of hydrofluoric acid salt dissolved in organic solvent (disclosed in Patent document 2).